EVE VetoCore FPGA / Silicon Partner Kit
The NDA-gated technical kit for serious FPGA, silicon, and enclave integration partners. The public Readiness Packet explains what runs today; this kit is the low-level material needed to bring the veto core to hardware — released only under NDA.
EVE VetoCore FPGA / Silicon Partner Kit
Veto core reference
veto_core.c and veto_interface.h — the pure deterministic veto and its C / firmware / HDL interface contract, plus the C↔Python equivalence harness.
Interlock + attestation
FPGA integration notes, the authenticated HMAC interlock protocol details, the hardware attestation runbook, and verifier internals for binding attestation into decision certificates.
Proof + scope
Conformance test vectors, the FPGA / silicon Statement of Work (PolarFire SoC bring-up, formal proofs), and a partner evaluation package.
What this kit is — and is not
EVE CoreGuard enforces deterministic, fail-closed governance in software today. The veto core is FPGA-compilable, and FPGA / enclave / HSM deployment is on the roadmap. This kit is the material a partner needs to execute that hardware phase.
It does not include production bitstreams, signing keys, root keys, HSM configuration, tenant-isolation internals, or a deployable “fuse-to-chip” package. Those remain EVE NeuroSystems IP and are not distributed.
Request the Partner Kit
The kit is released to qualified partners under a mutual NDA. Tell us who you are and what you're evaluating, and we'll start the NDA and partner-eval process.
Prefer the overview first? Download the public Readiness Packet (PDF, 15 pages) — no signup required.